1. Field of the Invention
The present invention relates to a voltage detecting circuit, and more specifically, to a voltage detecting circuit capable of accurately detecting a voltage even when a power source voltage is decreased.
2. Description of the Related Art
In portable information devices such as portable phones and mobile PCs, or systems such as car navigation systems, power is supplied by storage batteries. Such a power source device, which is charged to be used, is gradually discharged as a device having the power source device is used or in the course of time. As a result, the power source voltage is decreased. When the power source voltage is decreased to be lower than a predetermined level, the device cannot be operated normally. Conventionally, the power source voltage decreased to be lower than the predetermined level has been detected and a warning to charge the storage battery and the like has been given to a user. To realize such functions, a voltage detecting circuit capable of detecting a power source voltage has been used. By using the voltage detecting circuit, the power source voltage is detected as required and various processes can be performed based on the detected power source voltage.
FIG. 10 shows a general purpose voltage detecting circuit. In the circuit shown in FIG. 10, reference numeral 101 denotes a power source capable of supplying a voltage to be detected. That is, in this voltage detecting circuit, a voltage between terminals 102 and 103 is detected. Voltage dividing resistors 104 and 105 are connected between the terminals 102 and 103. The voltage between the terminals 102 and 103 is divided by the voltage dividing resistors 104 and 105, and inputted to a non-inverting input terminal of a comparator 106. On the other hand, a reference voltage is supplied from a power source 107 to an inverting input terminal of the comparator 106. An output terminal of the comparator 106 is connected to an inverter 108. An output terminal of the inverter 108 is connected to a common gate terminal of a PMOS transistor 109 and an NMOS transistor 110. The PMOS transistor 109 and the NMOS transistor 110 form an output circuit 111. Drain terminals of the PMOS transistor 109 and the NMOS transistor 110, which are connected function as an output terminal 112. In this voltage detecting circuit, a voltage at a connection between the voltage dividing resistors 104 and 105 and the reference voltage of the power source 107 are compared by the comparator 106. By detecting an inversion of an output voltage of the comparator 106, it is detected that the power source voltage 101, that is an input voltage, is decreased to be lower than a predetermined level.
In such a voltage detecting circuit, an output voltage of the output circuit 111 becomes unstable when an applied voltage is not higher than an operational voltage. Each of the PMOS transistor 109 and the NMOS transistor 110 forming the output circuit 111 is turned on when a voltage as high as or higher than its threshold voltage is applied between its gate and its source. When the power source voltage 101 is decreased, however, an operation of a differential amplifier circuit included in the comparator 106 becomes unstable. Therefore, operations of the PMOS transistor 109 and the NMOS transistor 110 become unstable, which makes it impossible to obtain a correct originally output voltage.
In view of this, there is a voltage detecting circuit disclosed in Patent Document 1, which operates correctly even when a power source voltage is decreased. FIG. 11 shows a voltage detecting circuit disclosed in Patent Document 1. In FIG. 11, a second output circuit 115 formed of a depletion mode NMOS transistor 113 and a depletion mode PMOS transistor 114 is provided in a subsequent stage after the output circuit 111 of FIG. 10. The depletion mode PMOS transistor 114 has a gate terminal connected to a positive electrode (terminal 102) of a power source to be detected while the depletion mode NMOS transistor 113 has a gate terminal connected to a negative electrode (terminal 103) of the power source to be detected. The depletion mode PMOS transistor 114 and the depletion mode NMOS transistor 113 are connected in series between the output terminal 112 and the terminal 103. As a result, even when the power source voltage 101 is decreased, the voltage level of the output terminal 112 can be held low or high and the output voltage can be prevented from becoming unstable.
[Patent Document 1] Japanese Patent Application Publication No. 2004-163315
In the voltage detecting circuit shown in FIG. 11, however, there is a problem in that a threshold value of each transistor cannot be easily controlled due to manufacturing reasons since the P-type depletion mode MOS transistor 114 and the N-type depletion mode MOS transistor 113 are used.